For data transmission between two system controllers, a buffer device for providing hardware synchronism and speed adjustment is usually provided between these controllers.
In a prior art data transmission system, such a buffer device as mentioned above is provided in single so that access from one controller has a preference over access from the other to avoid access collision.
With such a prior art arrangement, however, in the case where data transmission is intended from a system controller A to a system controller B and a write request from the controller A is set to have a preference over a read request from the controller B for example, there occurs such a problem that the write request during the reading operation causes different data before and after the reading, which results in that the controller B cannot handle the data of the controller A at the same time and having the contents as the controller B.
Even in the case where a dual port memory is used, this is a big problem when a package of data is transmitted from the system controller A to the system controller B, that is, accurate data transmission cannot be achieved.
In this type of data transmission, the system controllers A and B usually use mutually different system clocks. For this reason, a write request from the controller A and a read request from the controller B may be generated exactly simultaneously in synchronism with the different system clocks, in which case the write and read requests to the same memory collide with each other.
In view of the such circumstances, it is an object of the present invention to provide an asynchronous data transmission system which can accurately and reliably transmit a large quantity of data in the form of a single package between system controllers without any handshake.
Another object of the present invention is to provide an asynchronous data transmission system which can realize accurate and reliable data transmission between two system controllers having different system clocks.